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August 31, 2021
The Open Compute Summit just keeps getting bigger and better. By the numbers, the two-day event held in Santa Clara in mid-January this year drew three times the crowd of the 2012 gathering - amounting to more than 1,500 attendees! I could barely get a hotel room in the area due to the large number of people coming in for this event.
The summit is a meeting place for the people and organizations that support the Open Compute Project, an initiative announced by Facebook in April 2011 to openly share data center designs across the industry. And with the growth of this summit, it was clear that end users and vendors alike are getting involved and sharing ideas to make this a reality.
At the event, Intel (a founding member of the Open Compute Project) announced our collaboration with Facebook where we are defining next-generation rack technologies and how we will enable these technologies through Open Compute. As part of this collaboration, our two companies unveiled a mechanical prototype, built by Quanta Computer, that includes Intel’s new and innovative photonic rack architecture. This prototype showed the cost, design and reliability improvement potential of a disaggregated rack environment using Intel processors and SoCs, distributed switching with Intel switch silicon, and interconnects based on Intel silicon photonics technologies (green cables in photo below).
That’s the big picture—and the big news. Let’s now drill down into some of all-important details that shed light on what this announcement means in terms of the future of data center rack technologies.
Rack disaggregation refers to the separation of resources that currently exist in a rack, including compute, storage, networking and power distribution, into discrete modules. Traditionally, a server within a rack would each have its own group of resources. When disaggregated, resource types can then be grouped together, distributed throughout the rack, and upgraded on their own cadence without being coupled to the others. This provides increased lifespan for each resource and enables IT managers to replace individual resources instead of the entire system. This increased serviceability and flexibility drives improved total cost for infrastructure investments as well as higher levels of resiliency. There are also thermal efficiency opportunities by allowing more optimal component placement within a rack.
Intel’s photonic rack architecture, and the underlying Intel silicon photonics technologies, will be used for interconnecting the various computing resources within the rack. We expect these innovations to be a key enabler of rack disaggregation.
Today’s optical interconnects typically use an optical connector called MTP. The MTP connector was designed in the mid-1980s for telecommunications and not optimized for data communications applications. At the time, it was designed with state-of-the-art materials manufacturing techniques and know-how. However, it includes many parts, is expensive, and is prone to contamination from dust.
The industry has seen significant changes over the last 25 years in terms of manufacturing and materials science. Building on these advances, Intel teamed up with Corning, a leader in optical fiber and cables, to design a totally new connector that includes state-of-the-art manufacturing techniques and abilities; a telescoping lens feature to make dust contamination much less likely; with up to 64 fibers in a smaller form factor; fewer parts - all at less cost.
The mechanical prototype includes not only Intel silicon photonics technology, but also distributed input/output (I/O) using Intel Ethernet switch silicon, and supports Intel Xeon processor and next-generation system-on-chip Intel Atom processors code named “Avoton.”
These innovations are also aligned to Open Compute projects underway. The Avoton SOC/memory module was designed in concert with the writing of the CPU/memory “group hug” module specification that Facebook proposed to the OCP board work group at the summit. The existing OCP Windmill board specification (that supports the 2S Xeon processors) will be modified to show that the power and signal delivery to the board was modified to interface with the OCP Open Rack v1.0 specification (for power delivery through 12V bus bars) and for networking (to interface with a tray-level mid-plane board that holds the switch mezzanine module. Intel will also contribute a design for enabling a photonic receptacle to the Open Compute Project (OCP) and will work with Facebook*, Corning*, and others over time to standardize the design.
Intel has already delivered several innovations to the Open Compute Project and its working groups to enable future designs based on Intel Architecture. These innovations span board, system, rack, and storage technologies.
Here’s an example of how Open Compute Project investments are driving new technologies and products available on Intel Architecture.
In particular, Intel has been working with the OCP community to finalize the Decathlete board specification for a general-purpose, large-memory-footprint, dual-CPU motherboard for enterprise adoption. We expect that in 2013 several end users will be purchasing products from OEMs (Quanta & ZT Systems today) based on Decathlete. Intel also supported Wiwynn’s design efforts using the current Intel SoC roadmap to enable Knox Cold Storage (Centerton today, Avoton in the future).
To learn more about silicon photonics, see Intel's video, "How Silicon Photonics Works" and to hear more about silicon photonics potential impact on the data center, see Data Center Knowledge's story and video with Jeff Demain of Intel Labs, "Silicon Photonics: The Data Center at Light Speed." For a look at innovations driven by all the contributors to the Open Compute Project, visit the Specs & Designs section of the Open Compute Project website.
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